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Freescale Semiconductor Technical Data
MPC9894 Rev 3, 1/2005
Quad Input Redundant IDCS Clock Generator
The MPC9894 is a differential input and output, PLL-based Intelligent Dynamic Clock Switch (IDCS) and clock generator specifically designed for redundant clock distribution systems. The device receives up to four LVPECL clock signals and generates eight phase-aligned output clocks. The MPC9894 is able to detect failing clock signals and to dynamically switch to a redundant clock signal. The switch from the failing clock to the redundant clock occurs without interruption of the output clock signal (output clock slews to alignment). The phase bump typically caused by a clock failure is eliminated. The device offers eight low-skew clock outputs organized into four output banks, each configurable to support the different clock frequencies. The extended temperature range of the MPC9894 supports telecommunication and networking requirements. Features * * * * * * * * * * * * * * * * * * * * 8 differential LVPECL output pairs Quad-redundancy reference clock inputs IDCS-on-chip intelligent dynamic clock switch Smooth output phase transition during clock failover switch/* Automatically detects clock failures Clock activity monitor Clock qualifier inputs Manual clock select and automatic switch modes 21.25 - 340 MHz output frequency range Specified frequency and phase slew rate on clock switch LVCMOS compatible control inputs and outputs External feedback enables zero-delay configurations Output enable/disable and static test mode (PLL bypass) Low-skew characteristics: maximum 50 ps(1) output-to-output I2C interface for device configuration Low cycle-to-cycle and period jitter IEEE 1149.1 JTAG Interface 100-ball MAPBGA package Supports 2.5 V or 3.3 V supplies with 2.5 V and 3.3 V I/O Junction temperature range -40C to +110C
MPC9894
QUAD INPUT REDUNDANT IDCS CLOCK GENERATOR
VF SUFFIX 100-LEAD MAPBGA PACKAGE CASE 1462-01
Functional Description The MPC9894 is a quad differential redundant input clock generator. The device contains logic for clock failure detection and auto switching for clock redundant applications. The generator uses a fully integrated PLL to generate clock signals from any one of four redundant clock sources. The PLL multiplies the frequency of the input reference clock by one, two, four, eight or divides the reference clock by two or four. The frequency-multiplied clock signal drives four banks of two differential outputs. Each bank allows an individual frequency-divider configuration. All outputs are phase-aligned(1) to each other. Due to the external PLL feedback, the clock signals of all outputs are also phase-aligned(1) to the selected input reference clock, providing virtually zero-delay capability. The integrated IDCS continuously monitors all four clock inputs and indicates a clock failure for each clock input. When a false clock signal is detected on the active clock, the MPC9894 switches to a redundant clock input, forcing the PLL to slowly slew to alignment and not produce any phase bumps at the outputs. The MPC9894 also provides a manual mode that allows for user-controlled clock switches. The device is packaged in a 11x11 mm2 100-ball MAPBGA package.
1.
At coincident rising edges.
(c) Freescale Semiconductor, Inc., 2005. All rights reserved.
DEVICE DESCRIPTION
CLK0 CLK0 CLK1 CLK1 CLK2 CLK2 CLK3 CLK3
00 01 10 11 fcomp /P Comp PLL 340 - 680 MHz
1 /2, /4, /8, /16 0
QA0 QA0 QA1 QA1
/2, /4, /8, /16 /P FB /2, /4, /8, /16 IDCS
QB0 QB0 QB1 QB1 QC0 QC0 QC1 QC1
FB_IN FB_IN EX_FB_SEL CLK_VALID[3:0] CLK_ALARM_RST
/2, /4, /8, /16 PLL_BYPASS SCL SDA ADDR[0:2] MBOOT MEDIA PRESET MR JTAG[4:0] PLL_TST[2:0] TPA MSTROUT_EN Control Logic I2C Interface
QD0 QD0 QD1 QD1
/M/P
QFB QFB LOCK BUSY INT SEL_STAT[1:0] CLK_STAT[3:0]
Figure 1. MPC9894 Block Diagram
Table 1. Pin Configurations
Pin I/O Type Function Supply Active State Clock Inputs and Outputs CLK0, CLK0 CLK1, CLK1 CLK2, CLK2 CLK3, CLK3 FB_IN, FB_IN Input LVPECL PLL reference clock inputs (differential) (internal pulldown) VDDIC --
Input
LVPECL
PLL feedback signal input (differential). When configured for external feedback, the QFB output should be connected to FB_IN. (internal pulldown) Bank A differential outputs Bank B differential outputs Bank C differential outputs Bank D differential outputs Differential PLL feedback output. QFB must be connected to FB_IN for correct operation
VDDIC
--
QA[1:0], QA[1:0] QB[1:0], QB[1:0] QC[1:0], QC[1:0] QD[1:0], QD[1:0] QFB, QFB
Output Output Output Output Output
LVPECL LVPECL LVPECL LVPECL LVPECL
VDDAB VDDAB VDDCD VDDCD VDDCD
-- -- -- -- --
MPC9894 2 Advanced Clock Drivers Devices Freescale Semiconductor
Table 1. Pin Configurations (Continued)
Pin I/O Type Function Supply Active State Control Inputs and Outputs EX_FB_SEL CLK_VALID[3:0](1) CLK_ALARM_RST PLL_BYPASS MEDIA MR LOCK CLK_STAT[3:0] SEL_STAT[1:0] BUSY MBOOT PRESET INT MSTROUT_EN SEL_2P5V I2 C Interface I/O I/O Input OD OD LVCMOS I2C interface control, clock I2C interface control, data I2 C interface address lines (10K pullup) VDD VDD VDD VDDIC VDDIC VDDIC VDDIC VDDIC N/A VDDA -- -- -- -- -- -- -- -- high Input Input Input Input Input Input Output Output Output Output Input Input Output Input Input LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS OD LVCMOS LVCMOS Selects between external feedback and internal feedback Validates the clock inputs CLK0 to CLK3 (internal pullup) Reset of all four alarm status flags and clock selection status flag (internal pullup) Select static test mode (internal pulldown) Output impedance control Device reset (internal pullup) PLL lock indicator Clock input status indicator Reference clock selection indicator IDCS switching activity indicator Activates I2C boot sequence (internal pulldown) VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD high high low high high low low high high low high high low high high
Enables Preset configuration of configuration registers on release of MR (internal pulldown) Indicate any status IDCS change Master Enable for all Outputs (internal pulldown) Device core power supply selection for VDD and VDDA
SCL SDA ADDR[2:0] IEEE 1149.1 and Test TMS TDI TDO TCK TRST PLL_TEST[2:0] TPA Power and Ground GND VDD VDDAB VDDCD VDDIC VDDA
Input Input Output Input Input Input Output
LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS
JTAG test mode select (10K pullup) JTAG test data input (10K pullup) JTAG test data output JTAG test clock JTAG test reset (10K pullup) PLL_TEST pins (factory use only, MUST BE CONNECTED TO GND) PLL Analog test pin (factory use only, LEAVE OPEN)
-- -- -- -- -- -- --
Supply Supply Supply Supply Supply Supply
Ground -- -- -- -- --
Negative power supply Positive power supply for the device core, output status and control inputs. (3.3 V or 2.5 V) Supply voltage for output banks A and B (QA0 through QB1) (3.3 V or 2.5 V) Supply voltage for output banks C and D (QC0 through QD1) and QFB (3.3 V or 2.5 V) Supply voltage for differential inputs clock inputs CLK0 to CLK3 and FB_IN (3.3 V or 2.5 V) Clean supply for analog portions of the PLL (This voltage is derived via a RC filter from the VDD supply)
-- -- -- -- ----
1. bit order = msb to lsb.
MPC9894 Advanced Clock Drivers Devices Freescale Semiconductor 3
Table 2. Function Table
Control Control Inputs PLL_BYPASS 0 PLL enabled. The input to output frequency relationship is according to Table 9 if the PLL is frequency locked. The associated clock input is considered to be invalid and usable CLK_STAT[3:0] and SEL_STAT[1:0] flags are reset: CLK_STAT[3:0] = 0000 and SEL_STAT[1:0] = 00. CLK_ALARM_RST is a one-shot function. PLL bypassed and IDCS disabled. The VCO output is replaced by the reference clock signal fREF. This is considered to be a test mode and clock monitoring and clock switching are disabled during this operation. The associated clock input is considered to be a valid usable clock input CLK_STAT[3:0] and SEL_STAT[1:0] flags are active Default 0 1
CLK_VALID[3:0] CLK_ALARM_RST
0 1
MR
1
Outputs enabled (active) Reset of data generators and output dividers. The MPC9894 requires reset at power-up and after any loss of PLL lock. Loss of PLL lock may occur when the external feedback path is interrupted. The length of the reset pulse should be greater than two reference clock cycles I2C read/write mode Normal Operation Selects internal feedback path Low output impedance (QA0 to QD1 and QFB) Selects 3.3 V for core VDD I2C boot mode Uses Configuration Register PRESET values on MR Selects external feedback path 50 output impedance (QA0 to QD1 and QFB) Selects 2.5 V for core VDD
MBOOT PRESET EX_FB_SEL MEDIA SEL_2P5V MSTROUT_EN Control Outputs LOCK(1) BUSY INT CLK_STAT[3:0] SEL_STAT[1:0]
(1)
0 0 0 0 0
All outputs disabled (synchronous with clock being low) All outputs enabled
PLL is locked The IDCS has initiated a clock switch. IDCS status has changed (indicates an assertion of CLK_STAT[3:0] or deassertion of LOCK) Associated clock input not valid Encoded value refer to Table 7
PLL is unlocked No clock switch currently performed No status change Associated clock input valid Encoded value refer to Table 7
1. The combined pins of LOCK = 1 and BUSY = 0 are used to indicate a catastrophic failure. Refer to PLL Out-of-Lock Conditions.
MPC9894 4 Advanced Clock Drivers Devices Freescale Semiconductor
OPERATING INFORMATION
Basic Functional Description The MPC9894 is a quad-redundancy IDCS clock generator. The redundancy feature allows automatic switching from the reference clock source to a secondary clock source on detection of a failed reference clock. The MPC9894 will detect and report a missing clock on any of its four inputs. Based upon the current IDCS mode setting and the qualifier input pins, the MPC9894 will switch to the next qualified secondary clock. The input clock sources, CLK0, CLK1, CLK2, and CLK3, are assumed to be the same frequency(1) but non-phaserelated sources. When a clock switch occurs, the phase alignment to the new clock source will occur over an extended time period, eliminating runt clock output pulses. The maximum rate of phase change is specified in the AC parameter Delta Period per Cycle(PER/CYC). The device uses a fully integrated PLL to generate clock signals from redundant clock sources. The PLL multiplies the input reference clock signal by a variety of values, including 0.25, 0.5, 1, 2, 4 or 8. For a complete list refer to Table 9. The frequency multiplied clock signal drives four independent output banks. Each output bank is phase-aligned to the input reference clock phase, providing virtually zero-delay capability(2). The configuration of the MPC9894 series of clock generators is performed through either the I2C interface or by the preset configuration mode. The I2C interface uses a 2 pin interface to transmit clock and data to and from a series of configuration and status registers in the MPC9894. Definitions IDCS: Intelligent Dynamic Clock Switch. The IDCS monitors the clock inputs CLK0, CLK1, CLK2, and CLK3. Upon a failure of the reference clock signal, the IDCS switches to a qualified secondary clock signal and the status flags are set. Reference clock signal: The input clock signal that is selected by the IDCS or IDCS_MODE[2:0] as the input reference to the PLL. Primary clock: The input clock signal selected by IDCS_MODE[2:0]. The primary clock may or may not be the reference clock, depending on IDCS mode and IDCS status. Secondary clock: The input clock signal which will be selected by the IDCS upon an automatic clock switch. Tertiary, Quaternary clocks: The input clock signals that will be selected by the IDCS, in turn, after the current secondary clock. This clock selection is based upon a round robin rotational sequence Manual IDCS mode: The reference clock input is selected by IDCS_MODE[0xx]. Automatic IDCS mode: The reference clock signal is determined by the IDCS. Selected clock: The SEL_STAT[1:0] flags indicate the reference clock signal. Qualified clock: The corresponding CLK_VALID[3:0] signal is logic high, the associated CLK_STAT status bit is logic high and no clock failure is present. Bit Ordering: The bit ordering convention used in this document for both pin and register documentation is NAME[7:0] where bit 7 is the most significant bit and 0 is the least significant bit.
1. Refer to Table 39 for clock frequency specification. 2. Using external feedback.
MPC9894 Advanced Clock Drivers Devices Freescale Semiconductor 5
DEVICE CONFIGURATION
I2C Configuration and I2C Addressing The MPC9894 is configured via a series of 8-bit registers. The bits in these registers allow a wide range of control over the operation of the MPC9894 clock generator. These registers are accessed via an I2C interface through which a 7-bit address is sent from the I2C master to select the specific I2C slave device being accessed. The address for this clock driver is found in the first of the MPC9894 I2C registers. The format of this address has a fixed most-significant four bits of binary 1101 while the least-significant 3 address bits are read from the 3 ADDR pins. This provides the capability to configure up to 8 clock devices on a single I2C interface. In addition, activation of the MBOOT pin on power-up or reset initiates an automatic boot sequence allowing the clock generators to be initialized from an I2C compatible EEPROM. In this case the MPC9894 becomes an I2C master and the Table 3. MPC9894 IDCS Configuration
IDCS_MODE [2:0] 000 001 010 011 100 101 110 111 1. For CLK_VALID[3:0] = 1111 and input clock validity. Automatic Description Manual Primary Clock CLK0 CLK1 CLK2 CLK3 CLK0 CLK1 CLK2 CLK3 Secondary Clock(1) n/a n/a n/a n/a CLK1 CLK2 CLK3 CLK0 Tertiary Clock n/a n/a n/a n/a CLK2 CLK3 CLK0 CLK1 Quaternary Clock n/a n/a n/a n/a CLK3 CLK0 CLK1 CLK2
configuration bits are filled by the information from the first 6 bytes of the EEPROM. This allows the clock to be configured without a controlling I2C bus master if desired. The PRESET pin allows the device to be configured without a I2C bus master. The detailed register descriptions are found in the section, I2C Interface and configuration/status register. IDCS MODE Configuration Three register bits are used to configure the MPC9894 in either an automatic clock switch mode or into a manual clock select mode. The three mode select bits are defined in Table 3. IDCS modes 000 through 011 allow manual selection between the four clock sources. IDCS modes 100 through 111 enable the automatic mode of the IDCS.
Automatic IDCS Mode In the automatic mode, the clock failure detection is enabled and the IDCS overwrites the selected clock on a clock failure. The IDCS operation requires PLL_BYPASS = 0 and IDCS_MODE[2] = 1. The reference clock is handled in a round robin method based upon clock validity and the qualification input CLK_VALID[3:0]: The qualification input is obtained from the four input pins, CLK_VALID[3:0]. If any of the CLK_VALID pins are low the associated clock input will be considered "unqualified" and thus not selected as a reference clock. Alternatively, if a clock input does not have a valid clock signal, it will not be selected and the next qualified and valid clock is selected as the reference clock. For example, if IDCS_MODE[2:0] = 100 (the IDCS is in automatic mode), CLK_VALID[3:0] = 1111 and CLK0, CLK1, CLK2, and CLK3 have valid input clock signals then CLK0 is the primary clock and CLK1 is the secondary clock. The IDCS selects the primary clock as the reference clock and the PLL will phase-lock the clock outputs to the CLK0 input. Upon the failure of CLK0 the IDCS will select CLK1 as the reference clock and initiate a switch, making CLK1 the reference clock and CLK2 the secondary clock. If CLK1 fails, the IDCS will switch to CLK2, etc. A de-asserted CLK_VALID[] pin disables the associated clock input as secondary clock. The associated clock input cannot be selected by the IDCS as secondary clock signal. For instance, if CLK0 is the primary clock and
1. See Clock Failure Detection.
CLK_VALID[3:0] = 1101, the IDCS will select CLK2 upon a clock failure of CLK0 (CLK1 is disabled by the CLK_VALID1 input, allowing external logic to control the IDCS switch logic). If a clock is the reference clock signal and its associated CLK_VALID signal is switched from `valid' to `invalid', the IDCS initiates a clock input switch, selecting the next available clock input (secondary clock). An invalid clock(1) signal triggers the associated clock status output (CLK_STAT[3:0]), independent of the primary and reference clock. These pins go set on a clock failure and remain set (sticky) until the CLK_ALARM_RST pin or the individual alarm reset bits (ALARM_RST[3:0]) are asserted. The CLK_STAT[3:0] outputs are mirrored in the device register 4 for I2C bus access. After each successful IDCS-commanded switch, the primary clock as set by IDCS_MODE[1xx] is no longer the reference clock. The user may reset the IDCS flags by asserting the individual ALARM_RST[3:0] bits after each IDCS-commanded switch. Activation of ALARM_RST[3:0] does not change the reference clock. A user-commanded change of the primary clock in automatic mode requires a write command to the IDCS_MODE[2:0] = 0xx bits (the primary clock and SEL_STAT[1:0] can be freely changed by setting IDCS_MODE[2:0] = 1xx). If the reference clock is not the primary clock, a write command to IDCS_MODE[2:0] = 1xx will cause the PLL to lock on the primary clock, given the new primary clock is a qualified clock.
MPC9894 6 Advanced Clock Drivers Devices Freescale Semiconductor
Table 4. Input Clock Qualifier and Status Flag
Input Clock CLK0 CLK1 CLK2 CLK3 Associated Input Qualifier(1) CLK_VALID0 CLK_VALID1 CLK_VALID2 CLK_VALID3 Associated Input Clock Status Flag Pin CLK_STAT0 CLK_STAT1 CLK_STAT2 CLK_STAT3 Register location Device register 5, bit 3 Device register 5, bit 4 Device register 5, bit 5 Device register 5, bit 6
1. The input qualifier logic can be enabled or disabled by setting the QUAL_EN bit in register 3.
Table 5. Input Clock Status CLK_STAT[3:0]
CLK_STAT[] 0 1 Description Clock input failure Clock input signal valid
Table 6. Clock Input Qualifier CLK_VALID[3:0]
CLK_VALID[] 0 1 Associated Input Clock Not qualified and will not be selected Qualified
The SEL_STAT[1:0] pins indicate which of the four input clocks is the current reference clock. In the automatic mode and In the case of the reference clock failure, the SEL_STAT Table 7. SEL_STAT[1:0]
SEL_STAT[1:0] 00 01 10 11
flag will indicate a reference clock different from the original primary clock selected by IDCS_MODE[2:0]. The CLK_STAT outputs are mirrored in register 5, bits 1:0 for I2C bus access.
Selected clock input CLK0 CLK1 CLK2 CLK3
If all four clock inputs are not qualified the VCO will slew to its lowest frequency. This condition will be indicated by the LOCK pin being de-asserted. The MPC9894 will remain in this state until an input clock is restored and the device is reset via the MR pin. Clock Failure Detection The MPC9894 clock failure detection is performed using an input clock amplitude check combined with an activity detector. The following conditions will trigger a failed clock status (CLK_STATn = 0) on any qualified clock (CLK_VALIDn = 1). These conditions are: 1. Either or both CLKx, CLKx are disconnected from the input clock source and open. 2. CLKx and CLKx are shorted together 3. Either or both CLKx or CLKx are shorted to GND 4. Both CLKx and CLKx are shorted to a power supply 5. Amplitude of CLKx or CLKx is less than VPP, OK (refer to AC specification, Table 39) In addition, the currently selected clock is checked by a phase-frequency detector after the input divider (P). This is
triggered by a phase step of mae(). This phase detector will issue a failed clock status (CLK_STATn = 0) within 'P' clock cycles. The IDCS does not detect changes of the reference frequency or the reference frequency being out of the specified input frequency range. This includes errors such as reference frequency drift due to crystal aging etc. Clearing of IDCS Alarm Flags The input clock status flags are set by a clock failure and remain set until manually cleared (sticky). Clearing can be done by either of two methods. All status flags can be cleared by the package pin, CLK_ALARM_RST. Or individual status flags can be cleared via register bits, ALARM_RST[3:0]. The CLK_ALARM_RST pin is activated by a negative edge on the pin. This clears all CLK_STAT[3:0] flags and returns the IDCS to the primary clock source. The SEL_STAT[1:0]-selected clock indicator now reflects the IDCS_MODE[2:0] setting. By using ALARM_RST[3:0] (register 2) individual CLK_STAT[3:0] bits are cleared by writing a logic 0 to the individual bit in this register. It is important to note that this action does not return the IDCS to the primary clock.
MPC9894 Advanced Clock Drivers Devices Freescale Semiconductor 7
IDCS Manual Mode The manual request IDCS mode is selected by IDCS_MODE[2:0] = 0xx. The PLL functions normally and all four inputs clocks are monitored. The reference clock will always be the clock signal selected by IDCS_MODE[1:0] and will be indicated by SEL_STAT[1:0]. A manual-requested clock switch (by changing the IDCS_MODE[0xx] signal) will only be executed if the new clock is valid. The SEL_STAT[1:0] pins/bits should be checked after the manual request to ensure the clock switch occurred. Interrupt Operation The MPC9894 pin, INT, may be used to interrupt a microprocessor or microcontroller. This open drain output pin goes active or low on any of the following occurrences 1. A clock failure as indicated by any of bits 6 thru 3 being set in the status register 2. A out-of-lock condition for the PLL as indicated by either the LOCK pin or bit 2 of the status register. The interrupted processor would then use the I2C interface to read the status register (bit 7) to determine if this MPC9894 generated the interrupt. If the interrupt was caused by this MC9894, the status register would then be analyzed to determine the reason for the interrupt and then the appropriate action taken. In order for interrupts to occur, the INT_E bit must be set in the Device Configuration and Output Clock Enable Register. Once the interrupt flag has been set, reading of the Status Register clears the INT flag. Clock Operation on Power-Up On or after power-up, the MPC9894 must be reset via the MR pin. The MPC9894 may be powered-up in either of three configurations. These configurations are selected by the PRESET pin and MBOOT pin. If PRESET is low, on release of the MR pin, the MPC9894 powers up in a benign mode with all clock outputs disabled. The device is ready to be and must be programmed via the I2C interface prior to operation. If the PRESET pin is high on the release of the MR pin, the MPC9894 powers up in a run state. In this case the IDCS is configured for automatic mode, CLK0 to be the primary clock, a divide by 2 on clock bank A and B outputs, a divide by 8 on clock C and D outputs, all clock output banks enabled and interrupts enabled. If using the preset mode, then at least one of the clock inputs must have the correct input frequency prior to MR going high.
Later in this document, tables defining the I2C interface registers describe both configurations. The default (reset) information is for the normal reset operation, while the default (preset) information describes the values for each configuration bit on activation of the PRESET pin. In order to return the MPC9894 to either the preset or reset configuration the MR pin must be activated. Refer to the Boot Mode for a description of the MBOOT pin. PLL Feedback The MPC9894 may be operated with either an internal or an external PLL feedback path. The selection of internal vs. external feedback is made with the pin, EX_FB_SEL. If external feedback is desired, the EX_FB_SEL pin should be connected to VDD and a connection from QFB/QFB to FB_IN/ FB_IN must be made. External feedback provides a known relationship between the clock input and the feedback input for phase synchronization of output clock signals to the clock input. If this phase synchronization is not required, the MPC9894 may be configured for internal feedback by the connection of EX_FB_SEL to ground. In this configuration, the connection from the feedback output to the feedback input is not required. The feedback output may be used as a separate output to produce a reference clock output. PLL Out-of-Lock Conditions The LOCK pin and associated status bit indicates the lock state of the PLL. After power-up and prior to writing configuration data to the control registers, an out-of-lock condition will be indicated by LOCK = 1. If a valid clock is available and proper configuration data is written to the control registers, LOCK will then indicate the PLL is in a locked condition with LOCK = 0. The combination of LOCK = 1 and BUSY = 0 is used to indicate a catastrophic failure of the PLL. This condition will occur on the following: 1. All input clocks have failed or no clock is present. 2. External feedback has been selected with the EX_FB_SEL pin and an external feedback signal is not present on the FB_IN/FB_IN inputs. It should be noted that if this condition occurs during the initial PLL lock acquisition the PLL will produce a clock that is locked to the internal feedback path. However, the catastrophic failure status of LOCK = 1 and BUSY = 0 will occur. Recovery from the catastrophic failure condition requires repairing the cause of the failure, followed by a master reset to be issued to the MPC9894.
MPC9894 8 Advanced Clock Drivers Devices Freescale Semiconductor
CLOCK OUTPUT TRANSITION
An MPC9894 clock switch, either in IDCS manual or IDCS automatic mode, follows the next positive edge of the newly selected reference clock signal. The positive edge of the feedback clock and the newly selected reference clock edge will start to slew to alignment by adjusting the feedback edge placement a small amount of time in each clock cycle. Figure 2. Clock Switch shows a failed primary input clock with the MPC9894 switching to and aligning to the secondary clock. This small amount of additional time in each clock cycle will ensure that the output clock does not have any large phase changes or frequency changes in a short period of time. The alignment will be to either 1) the closest edge,
Primary Clock
either forward or backward or 2) toward the lagging clock edge. The maximum rate of period change is specified in the AC parameter tables with the parameter of PER/CYC. This parameter implies that the output clock edge will never change more than the specified amount in any one cycle. The busy signal is used to indicate that the MPC9894 is in the process of slewing to the new input clock alignment. The signal is accessed thru the BUSY pin and goes set upon a clock switch. The pin is reset once the phase realignment is completed. During the period that BUSY is active, the configuration register of the MPC9894 should not be written with new configuration data.
Secondary Clock Output Clock BUSY BUSY
Figure 2. Clock Switch For example, if the current input clock of 62.5 MHz and the secondary clock are 180 degrees out of phase then the minimum clock transition time can be calculated by tcycle = 1 / fcycle = 1 / 62.5 MHz = 16 ns Therefore 180 degree clock difference is Assuming a PER/CYC of 40 ps, then tcycle / 2 = 8 ns The alignment to the closest edge ensures re-alignment to the new clock input in the minimum time. c. In applications where the input clocks are closely aligned, there is no ambiguity on the direction of clock slew. d. The clock output frequency will either increase or decrease based on direction of clock slew. 2. Slew to lagging edge a. The output frequency always decreases. Thus the clock frequency never violates a maximum frequency specification in the user system. b. When input clocks are closely aligned (within SPO + jitter) the MPC9894 may align to the closest edge or to the lagging edge. In the case of multiple MPC9894s with equivalent clock inputs one MPC9894 may align in one direction while an other MPC9894 may align to the opposite direction. If default values for the Slew_Control is not the configuration desired then the reconfiguration of the slew method should be perform soon after power-up and the configuration should remain fixed from that point. b.
8ns / 40 ps/cycle = 200 cycles. This is the minimum number of cycles that will be required for the alignment to the new clock. The alignment to the new clock phase may occur slower than this but never faster. The alignment on clock failure is selectable between either 1) the closest edge, either forward or backward or 2) toward the lagging clock edge. The selection of the alignment method is selected in the Slew_Control bit (bit 5) of the Device Configuration and Output Enable Register. This selection allows the user to select the alignment method that best suits the application. The characteristics and subsequent advantages and disadvantages of each method are described as follows. 1. Slew to closest edge a. The alignment is either forward toward the lagging edge or backward toward the leading edge.
MPC9894 Advanced Clock Drivers Devices Freescale Semiconductor 9
INPUT AND OUTPUT FREQUENCY CONFIGURATION
Configuring the MPC9894 input and output frequencies requires programming the internal PLL input, feedback and output dividers. The output frequency is represented by the following formula: fOUT = [(fREF / P) M] / N where fREF is the reference frequency of the selected input clock source (reference input), M is the PLL feedback divider and N is an output divider. The PLL input divider P, the feedback divider M and the output divider are configured by the device registers 1 and 4. The MPC9894 has four output Table 8. Configuration of PLL P, M and N Frequency Dividers
Divider PLL Input Divider (P) PLL Feedback Divider (M) PLL Output Divider, Bank A (NA) PLL Output Divider, Bank B (NB) PLL Output Divider, Bank C (NC) PLL Output Divider, Bank D (ND) /8, /12, /16 /2, /4, /8, /16 /2, /4, /8, /16 /2, /4, /8, /16 /2, /4, /8, /16 FSEL_B[1:0], Register 1, bit 7:6 FSEL_B[1:0], Register 1, bit 5:4 FSEL_C[1:0], Register 1, bit 3:2 FSEL_D[1:0], Register 1, bit 1:0 Available Values /1, /2, /3, /4, /6 Configuration Through Input_FB_Div[3:0], Register 4, bit 3:0
banks (Bank A, B, C, and D) and each output bank can be configured individually as shown in Table 8.
fREF /P /N fOUT
PLL
/M
Figure 3. PLL Frequency Calculation
The reference frequency fREF and the selection of the PLL input divider (P) and feedback-divider (M) is limited by the specified VCO frequency range. fREF, P and M must be configured to match the VCO frequency range of 340 to 680 MHz in order to achieve stable PLL operation: fVCO,MIN (fREF / P M) fVCO,MAX The PLL input divider (P) can be used to situate the VCO in the specified frequency range. The PLL input divider effectively extends the usable input frequency range.
The output frequency for each bank can be derived from the VCO frequency and output divider (N): fQA[1:0] = fVCO / NA fQB[1:0] = fVCO / NB fQC[1:0] = fVCO / NC fQD[1:0] = fVCO / ND Table 9 illustrates the possible input clock frequency configurations of the MPC9894. Note that the VCO lock range is always 340 MHz to 680 MHz, setting lower and upper boundaries for the frequency range of the device.
Table 9. Input and Output Frequency Ranges
Input_FB_Div[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 4 6 /8 /12 170.0 - 340.0 170.0 - 340.0 1fREF 1fREF /4 /12 113.32 - 226.64 1.5fREF reserved reserved reserved 0.5fREF 0.5fREF 0.25fREF 0.25fREF 0.125fREF 0.125fREF /2 /3 /4 /8 /12 /16 85.0 - 170.0 85.0 - 170.0 85.0 - 170.0 2fREF 2fREF 2fREF reserved 0.75fREF 0.375fREF 0.1875fREF P /1 /1 /2 /1 /2 M /16 /12 /12 /8 /16 fREF range MHz 21.25 - 42.5 28.33 - 56.67 56.66 - 113.34 42.5 - 85.0 42.5 - 85.0 Output frequency for any bank A, B, C or D (FSEL_x) and ratio to fREF N=2 8fREF 6fREF 3fREF 4fREF 4fREF reserved 1fREF 1fREF 1fREF 0.5fREF 0.5fREF 0.5fREF 0.125fREF 0.125fREF 0.125fREF N=4 4fREF 3fREF 1.5fREF 2fREF 2fREF N=8 2fREF 1.5fREF 0.75fREF 1fREF 1fREF N = 16 fREF 0.75fREF 0.375fREF 0.5fREF 0.5fREF
MPC9894 10 Advanced Clock Drivers Devices Freescale Semiconductor
I2C INTERFACE AND CONFIGURATION/STATUS REGISTERS
The following tables summarize the bit configurations for the registers accessible via the I2C interface. The register values are read or written over the I2C interface by the I2C Master. This sequence starts with the I2C start command, followed by the I2C device address and read/write byte. This is then followed by the address of the register that is to be accessed. In the case of a write, the register address byte is followed by the data to be written to that register. In the case Table 10. I2C Registers
Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 Register Table 11. Slave Address (Register 0 -- Read Only) Table 12. Output Configuration Register (Register 1 -- Read/Write) Table 14. Mode Configuration and Alarm Reset Register (Register 2 -- Read/Write) Table 17. Device Configuration and Output Clock Enable Register (Register 3 -- Read/Write) Table 22. Input and Feedback Divider Configuration Register (Register 4 -- Read/Write) Table 24. Status Register (Register 5 -- Read Only) Table 25. Output Power-Up Register (Register 6 -- Read/Write) Table 27. Feedback Power-Up Register (Register 7 -- Read/Write)
of a read, the device will then respond with the data from that register. At the conclusion of the transfer an I2C Stop command is issued by the Master to terminate the transfer. For a complete description of the I2C protocol refer to the v2.1 I2C specification. Table 10 lists the registers that are accessible via the I2C interface.
Boot Mode When the I2C boot mode is activated on power-up or reset via the MBOOT pin, the entire set of writable configuration registers are written with a 6-byte sequence. This sequence starts with the Output Configuration Register, and is followed by the Mode Configuration and Alarm Reset Register, the Device Configuration and Output Clock Enable Register, the Input and Feedback Divider Configuration Register, the Output Power-Up Register and the Feedback Power-Up Register. This equates to the register sequence of 1, 2, 3, 4,
ACK Dev Selection Start Byte Addr Write
6, 7. This sequence starts with the start command, the device select and read/write(write) byte, followed by the beginning byte address for reading from the EEPROM. This is then followed by the start command, device select and read/write (read) and four current address read bytes. The device address is the binary 7-bit value of 1010000. This I2C sequence is compatible with industry standard I2C bus EEPROMs such as STMicroelectronics M24C01, or equivalent.
ACK Dev Selection Start
ACK Data Out Read
NoACK
Stop
Figure 4. Boot Mode Random Access Read Slave Address Register The Slave Address register contains the I2C address that is used to determine if the data on the I2C interface is addressed to this device. The seven-bit address is determined with the fixed value of binary 1101 followed by Table 11. Slave Address (Register 0 -- Read Only)
Bit Description 7 not used 6 ADDR_6 5 ADD_R5 4 ADDR_4 3 ADDR_3 2 ADDR_2 read from ADDR[2] pin 1 ADDR_1 read from ADR[1] pin 0 ADDR_0 read from ADDR[0] pin
variable bits that are obtained from the three address pins. The three input pins allow for 8 different addresses for a given clock generator, allowing up to 8 clock generators to be addressed on a single I2C interface.
Reset default Preset default
1 1
1 1
0 0
1 1
MPC9894 Advanced Clock Drivers Devices Freescale Semiconductor 11
Output Configuration Register The output configuration register is divided into four, 2 bit-groups with each group selecting the divide ratio for
output banks A through bank D, refer to Table 12. For each bank, four output divider settings (/2, /4, /8, /16) are available, refer to Table 12.
Table 12. Output Configuration Register (Register 1 -- Read/Write)
Bit Description Reset default Preset default 0 0 7 FSEL_A[1:0] 0 0 0 0 6 5 FSEL_B[1:0] 0 0 0 1 4 3 FSEL_C[1:0] 0 0 0 1 2 1 FSEL_D[1:0] 0 0 0
Table 13. PLL Output Divider N (FSEL_A to FSEL_D)
FSEL_x[1:0] 00 01 10 11 Value /2 /4 /8 /16
Mode Configuration Register The mode configuration register, refer to Table 14, is a read/write register and contains the fields for mode selection as well as alarm reset. The mode of the MPC9894 may be changed by writing the three least significant Mode Configuration Register bits to the desired value. The current idcs mode of the MPC9894 may be obtained by reading this register. The alarm reset bits, found in bit positions 6 thru 3, may be used to individually reset the status flags of register 5. Each
of these flag bits are associated with the four clock inputs pins and indicate a failed clock input. Clearing of a clock status flag is performed by writing a logic 1 to the individual bit (or bits if more than one flag is to be cleared). Care should be taken to insure that the idcs mode information is written to the proper value when resetting the clock status bits. The four alarm reset bits always read as a logic 0. If a clock input status flag is cleared and the clock input is still in a failed state, the status flag will go set within 4 clock cycles after being cleared.
Table 14. Mode Configuration and Alarm Reset Register (Register 2 -- Read/Write)
Bit Description Reset default Preset default 7 not used n/a n/a n/a n/a 6 5 4 3 2 1 0 ALARM_RST[3:0] (Refer to Table 15) n/a n/a n/a n/a n/a n/a IDCS_MODE[2:0] (Refer to Table 16) 0 1 1 0 1 0
Table 15. Individual Reset of CLK_STAT[x] Bits
ALARM_RST[x] 0 1 No action The status flag CLK_STAT[x] is cleared by setting of this bit. (bit always reads as zero) Description
Table 16. MPC9894 IDCS Configuration(1)
IDCS_MODE [2:0] 000 001 010 011 100 101 110 111 1. This is a repeat of Table 8. 2. For CLK_VALID[3:0] = 1111 and input clock validity. Automatic Description Manual Primary clock CLK0 CLK1 CLK2 CLK3 CLK0 CLK1 CLK2 CLK3 Secondary clock(2) n/a n/a n/a n/a CLK1 CLK2 CLK3 CLK0 Tertiary clock(2) n/a n/a n/a n/a CLK2 CLK3 CLK0 CLK1 Quaternary clock(2) n/a n/a n/a n/a CLK3 CLK0 CLK1 CLK2
MPC9894 12 Advanced Clock Drivers Devices Freescale Semiconductor
Device Configuration and Output Enable Register The Device Configuration and Output Enable Register is used to individually enable or disable each bank of outputs. Output banks are enabled by setting the corresponding bit to a logic 1 and disabled by setting the bit to a logic 0 as described in Table 21. Output Clock Stop/Enable. The disable logic sets the outputs of the addressed bank synchronously to logic low state (Qx[] = 0 and Qx[] = 1). The clock output enable/stop bits can be set asynchronous to any clock signal without the risk of generating of runt pulses. The
PLL feedback output QFB cannot be disabled when MPC9894 is configured for external feedback. The Device Configuration Register, bit 6, QUAL_EN is used to enable or disable all clock input qualifier pins. Asserting this bit enables the Clock Qualifier Input Pins CLK_VALID[3:0]. Deasserting this bit disables these pins such that inputs on CLK_VALID[3:0] are ignored. The INT_E bit, in bit position 7, is used to enable or disable interrupts from occurring on the INT pin. The setting of the interrupt flag (bit 7 of the Status Register) is unaffected by this bit.
Table 17. Device Configuration and Output Clock Enable Register (Register 3 -- Read/Write)
Bit Description Reset default Preset default 7 INT_E 0 1 6 QUAL_EN 0 1 5 Slew_Control 0 0 4 Enable_QFB 0 0 3 ENABLE_QA 0 1 2 ENABLE_QB 0 1 1 ENABLE_QC 0 1 0 ENABLE_QD 0 1
Table 18. Interrupt Signal (INT) Enable INT_E
INT_E 0 1 Description Interrupt signal INT is disabled Interrupt signal INT is enabled
Table 19. Input Clock Qualifier Enable QUAL_EN
QUAL_EN 0 1 Description CLK_VALID[3:0] are disabled (clock qualifier signals are disabled) CLK_VALID[3:0] are enabled (clocks can be qualified)
Table 20. Slew Control
Slew_Control 0 1 Description Clock slew direction on clock switch is toward the closest edge Clock slew direction on clock switch is toward the lagging edge
Table 21. Output Clock Stop/Enable
ENABLE_Qx 0 1 Description Output bank x is disabled (clock stop in logic low state) Output bank x is enabled
MPC9894 Advanced Clock Drivers Devices Freescale Semiconductor 13
Input and Feedback Divider Configuration Register Table 22. Input and Feedback Divider Configuration Register (Register 4 -- Read/Write)
Bit Description Reset default Preset default 7 Reserved n/a n/a 6 Reserved n/a n/a 5 Reserved n/a n/a 4 Reserved n/a n/a 0 0 3 2 1 0 Input_FB_Div[3:0] 0 0 0 1 0 1
The Input and Feedback Divider Configuration Register is used to select the input divider value and the feedback divider values. The four bits for Input_FB_Div allow 16 combinations of input and feedback divider ratios. Some input and output Table 23. Input_FB_Div[3:0]
Input_FB_Div[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 4 6 4 2 3 4
frequency ranges may overlap allowing a choice of PLL closed loop bandwidths. This selection may be useful when PLL devices are cascaded.
Input Divider (P) 1 1 2 1 2 reserved
Feedback Divider (M) 16 12 12 8 16
8 12 16 reserved 12 reserved reserved reserved 8 12
Device Status Register The Device Status Register contains a copy of the status SEL_STAT[1:0], LOCK and CLK_STAT[3:0] pins. In addition, bit 7 is an INT flag bit, which is used to indicate a setting of a bit in the CLK_STAT[3:0], a clearing of the LOCK bit and a change in the value of the SEL_STAT[1:0] bits. Table 24. Status Register (Register 5 -- Read Only)
Bit 7 6 5 4
The CLK_STAT[3:0] bits are sticky and remain set until manually reset through the Mode Configuration Register. The setting of the register INT bit is reflected on the interrupt pin only if interrupts are enabled. Enabling interrupts is done by the setting of the INT_E bit which is located in the Device Configuration Register. Reading of the Status Register clears the INT flag.
3
2 LOCK Inverse of LOCK signal
1
0
CLK_STAT[3:0] Description INT Inverse of INT Status of CLK3, CLK2, CLK1 and CLK0 (sticky) Copy of CLK_STAT[3:0] signal signal
SEL_STAT[1:0] Copy of SEL_STAT[1:0] signal
MPC9894 14 Advanced Clock Drivers Devices Freescale Semiconductor
Output Power-Up Register The Output Power-Up Register configures each of the 8 LVPECL outputs for either power-up or a power-down state. The use of these bits allows power consumption to be
reduced when all of the clock outputs are not used. Placing an output in the power-down condition is not synchronous with the clock edges.
Table 25. Output Power-Up Register (Register 6 -- Read/Write)
Bit Description Reset Default Preset Default 7 PWR_QD1 0 1 6 PWR_QD0 0 1 5 PWR_QC1 0 1 4 PWR_QC0 0 1 3 PWR_QB1 0 1 2 PWR_QB01 0 1 1 PWR_QA1 0 1 0 PWR_QA0 0 1
Table 26. Clock Output Power-Up Bits
PWR_Qxx 0 1 Output Power-Down Output Power-Up Description
Feedback Power-Up Register The Feedback Power-Up register bit 0 is used to configure the MPC9894 feedback output in either a power-up state or a power-down state. Note this register bit is valid for internal
feedback configuration only. When external feedback is selected QFB is always enabled and in a power-up state. The remaining bits of this register are unused and read as a logic 0.
Table 27. Feedback Power-Up Register (Register 7 -- Read/Write)
Bit Description Reset Default Preset Default 7 6 5 4 3 2 1 0 PWR_QFB 0 1
Table 28. Feedback Output Power-Up Bit
PWR_QFB 0 1 Feedback Output Power-Down Feedback Output Power-Up Description
MPC9894 Advanced Clock Drivers Devices Freescale Semiconductor 15
IEEE STD.1149.1(JTAG)
This section describes the IEEE Std. 1149.1 compliant Test Access Port (TAP) and Boundary Scan Architecture implementation in the MPC9894. Special private instructions are provided to assist in production test control. These instructions combined with control of the test mode inputs Table 29. TAP Interface Signals
Signal Name TCK TMS TDI TRST_B TDO Description Test Clock Test Mode Select Test Data In Test Reset Bar Test Data Out Function Test logic clock. TAP mode control input. Serial test instruction/data input. Asynchronous test controller reset. Serial test instruction/data output. Direction Input Input Input Input Output Active State -- -- -- -- --
and the use of shared inputs and outputs provide for full production test mode access and control. Test Access Port Interface Signals Table 29 lists the TAP interface signals and their descriptions.
Instruction Register Table 30. Instruction Register
Bit Position Field Capture-IR Value 0 0 4 3 2 IR 0 0 1 1 0
Instructions Table 31 lists the public instructions provided in the implementation and their instruction codes. Public Table 31. TAP Controller Public Instructions Instruction
BYPASS CLAMP EXTEST HIGHZ IDCODE SAMPLE
instructions are accessible by the customer for board test and may also be used for production chip test.
Code
11111 01100 00000 01001 00001 00010
Enabled Serial Test Data Path
Bypass Register Bypass Register Boundary Scan Register Bypass Register ID Register Boundary Scan Register
Boundary-Scan Register A full description of the boundary scan register may be found in the BSDL file. Device Identification Register (0x0281D01D) Table 32. Device Identification Register
Bit Position Field Value 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Version 0 0 0 0 0 1 0 1 0 Part Number 0 0 0 0 0 1 1 1 0 1 0 0 0 8 7 6 5 4 3 2 1 0
Manufacturer ID 0 0 0 0 1 1 1 0 1
MPC9894 16 Advanced Clock Drivers Devices Freescale Semiconductor
POWER SUPPLY CONFIGURATION
The MPC9894 operates from either a 3.3 V or 2.5 V voltage supply for the device core. The pin SEL_2P5V is used to logically indicate the core supply voltage. This selection is done by setting the pin to a logic 1 for 2.5 V or logic 0 for 3.3 V operation. The input and output supply voltage may be set for either 3.3 V or 2.5 V and can be individually set for inputs and banks Table 33. Power Supply Configuration
Supply Voltage VDD VDDAB VDDCD VDDIC VDDA
(1)
of outputs. Table 33. Power Supply Configuration lists the supply pins and what pin or group of pins are associated with each supply. Note, that for output skew and SPO specifications to be valid the input, feedback input and output, and the output bank must all be at the same voltage level.
Description Positive power supply for the device core, output status and control inputs. (3.3 V or 2.5 V) Supply voltage for output banks A and B (QA0 through QB1) Supply voltage for output banks A and B (QC0 through QD1) and QFB Supply voltage for differential inputs clock inputs CLK0 to CLK3 and FB_IN
Value 3.3 V or 2.5 V 3.3 V or 2.5 V 3.3 V or 2.5 V 3.3 V or 2.5 V
Clean supply for Analog portions of the PLL (This voltage is derived via an RC filter from the VDD supply) Derived from VDD
1. VDDIC (Supply of FB_IN) must be equal to VDDCD (Supply of QFB) to ensure the SPO specification is met.
Power Supply Sequencing and MR Operation Figure 5 defines the release time and the minimum pulse length for MR pin. The MR release time is based upon the power supply being stable and within VDD specifications. Refer to Table 39 for actual parameter values. The MPC9894
may be configured after release of reset and the outputs will be stable for use after lock indication is obtained. VDD must ramp up prior to or concurrent with the other power supply pins. It is recommended that the maximum slew rate for the VDD supply not exceed 0.5 V/ms.
VDD
MR treset_rel treset_pulse
Figure 5. MR Operation
VDD TBD RS VDDA TBD TBD VDD MPC9894
Figure 6. VCC Power Supply Bypass Power Supply Bypassing The MPC9894 is a mixed analog/digital product. The differential architecture of the MPC9894 supports low noise signal operation at high frequencies. In order to maintain its superior signal quality, all VCC pins should be bypassed by high-frequency ceramic capacitors connected to GND. If the spectral frequencies of the internally generated switching noise on the supply pins cross the series resonant point of an individual bypass capacitor, its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the noise bandwidth.
Clock Outputs The MPC9894 clock outputs are differential LVPECL voltage compatible. The outputs are designed to drive a single 50 impedance load that is properly terminated. The media pin is used to select between either of two output termination techniques. Selection of media = 0 sets all of the outputs to drive up to 50 parallel terminated (to VTT) transmission lines. With media = 1 the outputs are designed to drive 50 transmission line terminated with a single 100 differential load resistor. See Figure 7 and Figure 8 for diagrams of each of these termination techniques. Note, that the traditional output pulldown resistors for emitter follower biasing are not required for the MPC9894. If external feedback is used, the QFB output must be terminated with the same technique as selected with the media pin. Once a termination technique is chosen, that technique must be used for all MPC9894 outputs to guarantee output skew timing. The recommended termination technique is media = 1. This provides a simpler termination method and also reduces overall power consumption of the MPC9894. Unused outputs may be powered-down via the Output Power-Up and Feedback Power-Up registers to conserve power. If external feedback is selected the programming of the PWR_QFB bit is ignored.
MPC9894 Advanced Clock Drivers Devices Freescale Semiconductor 17
Table 34. Absolute Maximum Ratings(1)
Symbol VDD VDDAB, CD VDDIC VDDA VIN VOUT IIN IOUT TS Characteristics Supply Voltage (core) Supply Voltage (differential outputs) Supply Voltage (differential inputs) Supply Voltage (Analog Supply Voltage) DC Input Voltage(2) DC Output Voltage(3) DC Input Current DC Output Current Storage Temperature -65 Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 Max 4.0 4.0 4.0 VDD VDDx+0.3 VDDx+0.3 20 50 125 Unit V V V V V V mA mA C Condition
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. 2. VDDx references power supply pin associated with specific input pin. 3. VDDx references power supply pin associated with specific output pin.
Table 35. General Specifications
Symbol VTT MM HBM CDM LU JC TJ Characteristics Output Termination Voltage (LVPECL) ESD Protection (Machine Model) ESD Protection (Human Body Model) ESD Protection (Charged Device Model) Latch-Up Immunity Thermal Resistance (junction-to-ambient, junction-to-board, junction-to-case) Junction Temperature(1) -40 200 2000 500 200 49 110 Min Typ VDD - 2 Max Unit V V V V mA C/W C Condition LVPECL outputs
1. Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should be selected according to the application life time requirements (Refer to Application Note AN1545 for more information). The device AC and DC parameters are specified up to 110C junction temperature allowing the MPC9894 to be used in applications requiring industrial temperature range. It is recommended that users of the MPC9894 employ thermal modeling analysis to assist in applying the junction temperature specifications to their particular application.
Table 36. DC Characteristics (TJ = -40C to +110C)(1)
Symbol Characteristics Min Typ Max Unit Condition Supply Current for VDD = 2.5 V5% and VDDAB,CD = 2.5 V5% IDD IDDAB, CD IDDA IDDIC IDD IDDAB, CD IDDA IDDIC Maximum Supply Current (core) Maximum Supply Current, unterminated Maximum Supply Current (Analog Supply) Maximum Supply Current (I/O) MEDIA = 0 40 65 8.0 15 150 100 20 60 mA mA mA mA VDD pins VDDAB and VDDCD pins VDDA pin VDDIC pins VDD pins VDDAB and VDDCD pins VDDIN pins VDDIC pins
Supply Current for VDD = 3.3 V5% and VDDAB,CD = 3.3 V5% or VDDAB,CD = 2.5 V5% Maximum Supply Current (core) Maximum Supply Current, unterminated Maximum Supply Current (Analog Supply) Maximum Supply Current (I/O) MEDIA = 0 50 100 10 25 150 150 25 75 mA mA mA mA
1. DC characteristics are design targets and pending characterization.
MPC9894 18 Advanced Clock Drivers Devices Freescale Semiconductor
Table 37. PECL DC Characteristics (TJ = -40C to +110C)(1)
Symbol Characteristics Voltage(3) Min
FB_IN)(2)
Typ
Max
Unit
Condition
Differential PECL clock inputs (CLKx, CLKx and FB_IN, VPKPK VCMR IIN AC Differential Input Current(1) Differential Cross Point Voltage(4) Input
for VDDIC = 3.3 V 5% or VDDIC = 2.5 V 5% 1.3 VDD-0.3 100 V V A Differential operation Differential operation VPP = 0.8 V and VCMR = VDDL-0.7 V Termination 50 to VTT Termination 50 to VTT
0.2 1.25
Differential PECL clock outputs (QA0 to QD1 and QFB) for VDDAB,CD = 3.3 V 5% or VDDAB,CD = 2.5 V 5% VOH VOL Output High Voltage Output Low Voltage 3.3 2.5 Output Impedance Zdiff MEDIA = 0 MEDIA = 1 VDDAB,CD -1.2 VDDAB,CD -2.0 -1.9 50 80 VDDAB,CD -0.7 VDDAB,CD -1.5 -1.4 V V
ZOUT 1. 2. 3. 4.

See Figure 7 See Figure 8
DC characteristics are design targets and pending characterization. Clock inputs driven by PECL compatible signals. VPKPK is the minimum differential input voltage swing required to maintain AC characteristics. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification.
Table 38. LVCMOS I/O DC Characteristics (TJ = -40C to +110C)(1)
Symbol Characteristics Min Typ Max Unit Condition Single-ended LVCMOS inputs for VDD = 3.3 V 5% VIH VIL VOH VOL VIH VIL VOH VOL Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage 2.4 0.4 2.0 VDD + 0.3 0.8 V V V V LVCMOS LVCMOS IOH = -6 mA IOL = 6 mA LVCMOS LVCMOS IOH = -6 mA IOL = 6 mA
Single-ended LVCMOS inputs for VDD = 2.5 V 5% Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage 1.9 0.4 1.7 VDD + 0.3 0.7 V V V V
1. DC characteristics are design targets and pending characterization.
MPC9894 Advanced Clock Drivers Devices Freescale Semiconductor 19
Table 39. AC Characteristics (TJ = -40C to +110C)(1) (2)
Symbol Characteristics Min Typ Max Unit Condition VDD = 3.3 V 5%, VDDAB,CD,IC = 3.3 V 5% or VDDAB,CD,IC = 2.5 V 5% Input and output timing specification fREF Input reference frequency 21.25 28.33 56.66 42.5 85.0 113.32 170 42.5 56.67 113.34 85 170 226.68 340 340 340 /2 output /4 output /8 output /16 output
(5)
MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz % ppm ps ps % kHz
Input_FB_Div[3:0] = 0 Input_FB_Div[3:0] = 1 Input_FB_Div[3:0] = 2 Input_FB_Div[3:0] = 3,4 Input_FB_Div[3:0] = 6,7,8 Input_FB_Div[3:0] = 10 Input_FB_Div[3:0] = 14,15 PLL bypass
Input reference frequency in PLL bypass mode(3) fVCO fMAX VCO frequency range Output Frequency
(4)
680 340.0 170.0 85.0 42.5 60 5000
170.0 85.0 42.5 21.25 40
PLL locked
fREFDC fREFacc mae() tr, tf DC fI2C VPP VPP, OK VPP, NOK VO(P-P) t() tsk(O)
PER/CYC
Reference Input Duty Cycle Input Frequency Accuracy
Misaligned Edge Specification Output Rise/Fall Time Output duty cycle I2 C frequency range
600
47.5 50
1600
800 52.5 400
20% to 80%
Differential input and output voltages Differential input voltage(6) (peak-to-peak) (PECL) Differential input Differential input voltage(7) voltage(8) (peak-to-peak) (PECL) (peak-to-peak) (PECL) 0.3 0.8 0.3 0.1 1.3 V V V V
Differential output voltage (peak-to-peak) (PECL)
PLL and IDCS specifications Propagation Delay (static phase offset) CLKX, CLKX to FB_IN, FB_IN Output-to-output Skew within a bank(9) Output-to-output Skew across a bank(9) Rate of change of period(10) /2 output /4 output /8 output /16 output /2 output /4 output /8 output /16 output -100 150 50 100 +40 +80 +120 +160 ps ps ps slew_control = 1 PLL locked with external feedback selected
PER/CYC
Rate of change of period(11)
40 80 120 160
10
ps
slew_control = 0
Jitter and bandwidth specifications tJIT(CC) Cycle-to-cycle jitter RMS (1 ) ps N = 2, 2, 2, 2 N = 4, 4, 4, 4 N = 8, 8, 8, 8 N = 16, 16, 16, 16 N = 2, 2, 2, 2 N = 4, 4, 4, 4 N = 8, 8, 8, 8 N = 16, 16, 16, 16
15 tJIT(PER) Period Jitter RMS (1 ) 10
ps ps
15 tJIT() BW I/O Phase Jitter PLL closed loop bandwidth
(12)
ps ps MHz
RMS (1 ) 2
30
MPC9894 20 Advanced Clock Drivers Devices Freescale Semiconductor
Table 39. AC Characteristics (TJ = -40C to +110C)(1) (2)
Symbol Characteristics
(Continued)
Min Typ Max Unit Condition
VDD = 3.3 V 5%, VDDAB,CD,IC = 3.3 V 5% or VDDAB,CD,IC = 2.5 V 5%
MR and PLL Lock
tLOCK treset_ref treset_pulse 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12.
Maximum PLL Lock Time
MR hold time on power up MR hold time
10 2 100
s ps ns
AC characteristics are design targets and pending characterization. AC characteristics apply for parallel output termination of 50 to VTT. In bypass mode, the MPC9894 divides the input reference clock. The input reference frequency must match the VCO lock range divided by the total feedback divider ratio: fREF = (fVCO / M) N. All Input Clock frequencies must be within this value to guarantee smooth phase transition on input clock switch. VPP is the minimum differential input voltage swing required to maintain AC characteristics including tpd and device-to-device skew. VPP, OK is the minimum differential input voltage swing required for a valid clock signal. Above VPP, OK the input will be detected as a good clock (see IDCS). VPP, NOK is the maximum differential input voltage swing for a guaranteed bad clock. Below VPP, NOK the input will be detected as a failed clock (see IDCS). VDDAB = VDDCD Rate of period change is the maximum change of the clock output signal period T per cycle on a IDCS commanded switch. Rate of period change is the maximum change of the clock output signal period T per cycle on a IDCS commanded switch. -3 dB point of PLL transfer characteristics.
Differential Pulse Generator Z = 50
Z = 50
Z = 50
RT = 50 VTT
DUT MPC9894
RT = 50 VTT
Figure 7. MPC9894 AC Test Reference (Media = 0)
Differential Pulse Generator Z = 50
Z = 50
Z = 50
RT = 100 RT = 50 VTT DUT MPC9894
Figure 8 . MPC9894 AC Test Reference (Media = 1)
MPC9894 Advanced Clock Drivers Devices Freescale Semiconductor 21
MPC9894 Pin and Package Table 40. MPC9894 Pin Listing
Signal Name CLK0 CLK0 CLK1 CLK1 CLK2 CLK2 CLK3 CLK3 FB_IN FB_IN QA0 QA0 QA1 QA1 QB0 QB0 QB1 QB1 QC0 QC0 QC1 QC1 QD0 QD0 QD1 QD1 QFB QFB CLK_VALID3 CLK_VALID2 CLK_VALID1 CLK_VALID0 Description Clock0 Positive Input Clock0 Negative Input Clock1 Positive Input Clock1 Negative Input Clock2 Positive Input Clock2 Negative Input Clock3 Positive Input Clock3 Negative Input Feedback Clock Positive Input Feedback Clock Negative Input Positive Differential Clock Output Negative Differential Clock Output Positive Differential Clock Output Negative Differential Clock Output Positive Differential Clock Output Negative Differential Clock Output Positive Differential Clock Output Negative Differential Clock Output Positive Differential Clock Output Negative Differential Clock Output Positive Differential Clock Output Negative Differential Clock Output Positive Differential Clock Output Negative Differential Clock Output Positive Differential Clock Output Negative Differential Clock Output Positive Differential Clock Output Negative Differential Clock Output Qualifier for clock input CLK3 Qualifier for clock input CLK2 Qualifier for clock input CLK1 Qualifier for clock input CLK0 Direction Input Input Input Input Input Input Input Input Input Input Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Input Input Input Input Input Input Input I/O I/O Input Input Input Input Type LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Active State -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- High High High High Low High High -- -- -- -- -- Low Supply VDDIC VDDIC VDDIC VDDIC VDDIC VDDIC VDDIC VDDIC VDDIC VDDIC VDDAB VDDAB VDDAB VDDAB VDDAB VDDAB VDDAB VDDAB VDDCD VDDCD VDDCD VDDCD VDDCD VDDCD VDDCD VDDCD VDDCD VDDCD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD Pin D1 D2 E3 E2 F3 F2 G1 G2 C1 C2 K4 J4 K5 J5 K7 J7 K6 J6 A7 B7 A6 B6 A4 B4 A5 B5 A3 B3 F10 E10 E9 E8 F8 F9 E7 C9 C10 A9 B8 A8 D10
CLK_ALARM_RST Reset of all four alarm status flags and clock selection status flag PLL_BYPASS MEDIA SCL SDA ADDR2 ADDR1 ADDR0 MR Select PLL of static test mode Output impedance control (high = 50 ) I C Interface Control, Clock I C Interface Control, Data I2C Interface Control, Address 2 (MSB) I C Interface Control, Address 1 I C Interface Control, Address 1 (LSB) Device Master Reset
2 2 2 2
MPC9894 22 Advanced Clock Drivers Devices Freescale Semiconductor
Table 40. MPC9894 Pin Listing (Continued)
Signal Name LOCK CLK_STAT3 CLK_STAT2 CLK_STAT1 CLK_STAT0 SEL_STAT1 SEL_STAT0 BUSY MBOOT INT PRESET TMS TDI TRST TCK TDO SEL_2P5V MSTROUT_EN PLL_TEST2 PLL_TEST1 PLL_TEST0 TPA EX_FB_SEL VDD VDDA VDDAB VDDCD VDDIC GND Description PLL Lock Indicator Input CLK3 status indicator Input CLK2 status indicator Input CLK1 status indicator Input CLK0 status indicator Reference Clock Selection Indicator (MSB) Reference Clock Selection Indicator (LSB) IDCS switch activity indicator Activates I C Boot Sequence Indicates any status IDCS change Sets preset state JTAG Test Mode Select JTAG Test Data Input JTAG Test Reset Bar JTAG Test Clock JTAG Test Data Out Indicate core VDD level, (high = 2.5 V, low = 3.3 V) Enable all outputs in sync PLL Test Bit 2 PLL Test Bit 1 PLL Test Bit 0 (LSB) PLL Analog Test Pin Select feedback mode (high = external) Control Input, Status Output and Core Supply Analog Supply Supply for A and B bank outputs Supply for C and D bank outputs Supply for input clocks Control Input, Status Output and Core Ground
2
Direction Output Output Output Output Output Output Output Output Input Output Input Input Input Input Input Output Input Input Input Input Input Output Input Power Power Power Power Power Ground
Type LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS OD LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Analog LVCMOS -- -- -- -- -- --
Active State Low High High High High High High High High n/a High High -- Low -- -- -- High -- -- -- -- -- -- -- -- -- -- --
Supply VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDIC VDDIC VDD VDDIC VDDIC VDD VDD VDDAB VDDAB VDDCD VDDA VDD VDD VDDA VDDAB VDDCD VDDIC GND
Pin G10 H9 H10 G8 G9 K8 J8 J10 D8 D9 H7 D3 H1 H2 G3 J3 D7 K9 H4 G5 D5 E4 C7 A10, B9, C3, C8, G7, H8, J9, K10 E1 H6, J2, K2 A1, C4, C6 B2, H3, K1 A2, B1, B10, C5, D4, D6, E5, E6, F1, F4, F5, F6, F7, G4, G6, H5, J1, K3
MPC9894 Advanced Clock Drivers Devices Freescale Semiconductor 23
Table 41. MPC9894 Pin Diagram
1 2 3 4 5 6 7 8 9 10
A
VDDC
GND
QFB
QD0
QD1
QC1
QC0
ADDR0
ADDR2
VDD
B
GND
VDDIC
QFB
QD0
QD1
QC1
QC0
ADDR1
VDD
GND
C
FB_IN
FB_IN
VDD
VDDCD
GND
VDDCD
EX_FB_SEL
VDD
SCL
SDA
D
CLK0
CLK0
TMS
GND
PLL_TEST0
GND
SEL_2P5V
MBOOT
INT
MR
E
VDDA
CLK1
CLK1
TPA
GND
GND
MEDIA
CLK_ VALID0 CLK_ ALARM_ RST CLK_ STAT1
CLK_ VALID1 PLL_ BYPASS CLK_ STAT0 CLK_ STAT3
CLK_ VALID2 CLK_ VALID3
F
GND
CLK2
CLK2
GND
GND
GND
GND
G
CLK3
CLK3
TCK
GND
PLL_TEST1
GND
VDD
LOCK
H
TDI
TRST
VDDIC
PLL_TEST2
GND
VDDAB
PRESET
VDD
CLK_ STAT2
J
GND
VDDAB
TDO
QA0
QA1
QB1
QB0
SEL_STAT0
VDD
BUSY
K
VDDIC
VDDAB
GND
QA0
QA1
QB1
QB0
SEL_ STAT1
MSTROUT _EN
VDD
MPC9894 24 Advanced Clock Drivers Devices Freescale Semiconductor
MPC9894 PROGRAMMING MODEL
Table 42. Slave Address (Register 0 -- Read Only)
Bit Description 7 not used 6 ADDR_6 5 ADD_R5 4 ADDR_4 3 ADDR_3 2 ADDR_2 read from ADDR[2] pin 1 ADDR_1 read from ADR[1] pin 0 ADDR_0 read from ADDR[0] pin
Reset default Preset default
x (TBD) x (TBD)
x (TBD) x (TBD)
x (TBD) x (TBD)
x (TBD) x (TBD)
Table 43. Output Configuration Register (Register 1 -- Read/Write)
Bit Description Reset default Preset default 0 0 7 FSEL_A[1:0] 0 0 0 0 6 5 FSEL_B[1:0] 0 0 0 1 4 3 FSEL_C[1:0] 0 0 0 1 2 1 FSEL_D[1:0] 0 0 0
Table 44. Mode Configuration and Alarm Reset Register (Register 2 -- Read/Write)
Bit Description Reset default Preset default 7 not used n/a n/a n/a n/a 6 5 4 3 2 1 0 ALARM_RST[3:0] (See Table 15) n/a n/a n/a n/a n/a n/a IDCS_MODE[2:0] (See Table 16) 0 1 1 0 1 0
Table 45. Device Configuration and Output Clock Enable Register (Register 3 -- Read/Write)
Bit Description Reset default Preset default 7 INT_E 0 1 6 QUAL_EN 0 1 5 Slew_Control 0 0 4 Enable_QFB 0 0 3 ENABLE_QA 0 1 2 ENABLE_QB 0 1 1 ENABLE_QC 0 1 0 ENABLE_QD 0 1
Table 46I. nput and Feedback Divider Configuration Register (Register 4 -- Read/Write)
Bit Description Reset default Preset default 7 Reserved n/a n/a 6 Reserved n/a n/a 5 Reserved n/a n/a 4 Reserved n/a n/a 0 0 3 2 1 0 Input_FB_Div[3:0] 0 0 0 1 0 1
Table 47. Status Register (Register 5 -- Read Only)
Bit Description 7 INT Inverse of INT signal 6 5 4 3 2 LOCK Inverse of LOCK signal 1 0 CLK_STAT[3:0] Status of CLK3, CLK2, CLK1 and CLK0 (sticky) Copy of CLK_STAT[3:0] signal SEL_STAT[1:0] Copy of SEL_STAT[1:0] signal
Table 48. Output Power-Up Register (Register 6 -- Read/Write)
Bit Description Reset Default Preset Default 7 PWR_QD1 0 1 6 PWR_QD0 0 1 5 PWR_QC1 0 1 4 PWR_QC0 0 1 3 PWR_QB1 0 1 2 PWR_QB01 0 1 1 PWR_QA1 0 1 0 PWR_QA0 0 1
Table 49. Feedback Power-Up Register (Register 7 -- Read/Write)
Bit Description Reset Default Preset Default 7 6 5 4 3 2 1 0 PWR_QFB 0 1
MPC9894 Advanced Clock Drivers Devices Freescale Semiconductor 25
PACKAGE DIMENSIONS
11
A1 INDEX AREA
B C K
NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A. 4. DATUM A, SEATING PLANE, IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGING.
11
TOP VIEW
4X
0.2
SIDE VIEW
9X
1 0.5 5 0.35 A (1.18)
K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 100X 9X
1
1.7 MAX
0.43 0.29 0.5 0.55 0.45 0.25 0.10 3
M M
4
A
SEATING PLANE
100X
0.12 A
DETAIL K ABC A
ROTATED 90 CLOCKWISE
A1 INDEX AREA
BOTTOM VIEW
CASE 1462-01 ISSUE O
MPC9894 26 Advanced Clock Drivers Devices Freescale Semiconductor
NOTES
MPC9894 Advanced Clock Drivers Devices Freescale Semiconductor 27
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MPC9894 Rev. 3 1/2005

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